bd8be2e759
### What this PR does / why we need it?
1.Add the implementation of normal Aclnn operators: MoeCombineNormal,
MoeDispatchNormal, NotifyDispatch，and DispatchLayout.
- MoeCombineNormal: Implements the combine logic within MoE operations.
- MoeDispatchNormal: Implements the dispatch logic within MoE
operations.
- NotifyDispatch: Exchanges topk_idx information among different ranks
to calculate the device memory required for the dispatch stage.
- DispatchLayout: Used to calculate information related to the device
memory layout for the dispatch stage.
2.Provide PyTorch interfaces for normal operators—get_dispatch_layout,
dispatch_prefill, and combine_prefill—to be used for MoE communication
during the prefill stage in vLLM.
- get_dispatch_layout: Calculates information related to the device
memory layout for the dispatch operator, and is called before
dispatch_prefill.
- dispatch_prefill: Initiates the dispatch operation.
- combine_prefill: Initiates the combine operation.
### Does this PR introduce _any_ user-facing change?
No
### How was this patch tested?
The functionality has already been validated using the local Qwen model.
Test cases will be added after support for multi-NPU use cases in the CI
pipeline is finalized.
- vLLM version: v0.12.0
- vLLM main:
ad32e3e19c
Signed-off-by: shiro-zzzz <zhangdianhao@huawei.com>
23 lines
484 B
C
23 lines
484 B
C
#ifndef NOTIFY_DISPATCH_TILING_H
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#define NOTIFY_DISPATCH_TILING_H
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#include "kernel_tiling/kernel_tiling.h"
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struct NotifyDispatchInfo {
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uint32_t rankSize;
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uint32_t rankId;
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uint32_t localRankSize;
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uint32_t localRankId;
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uint32_t sendCount;
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uint32_t numTokens;
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uint32_t aivNum;
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uint64_t totalUbSize;
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};
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struct NotifyDispatchTilingData {
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Mc2InitTiling mc2InitTiling;
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Mc2CcTiling mc2CcTiling1;
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NotifyDispatchInfo notifyDispatchInfo;
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};
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#endif |