realliujiaxu 31682961af [Feat] enable hierarchical communication for mc2 ops on A2 (#3015) ...

Currently, when in A2, setting the environment variables
`HCCL_INTRA_PCIE_ENABLE=1` and `HCCL_INTRA_ROCE_ENABLE=0` can reduce
cross-machine communication traffic and significantly improve
communication performance.

For more details, please refer to
[document](https://www.hiascend.com/document/detail/zh/Pytorch/710/apiref/torchnpuCustomsapi/context/torch_npu-npu_moe_distribute_dispatch_v2.md)

- vLLM version: v0.11.0rc3
- vLLM main: https://github.com/vllm-project/vllm/commit/v0.11.0

---------

Signed-off-by: realliujiaxu <realliujiaxu@163.com>

2025-10-13 16:13:17 +08:00

..

e2e

Add models test and add serval new models yaml (#3394)

2025-10-12 17:27:50 +08:00

ut

[Feat] enable hierarchical communication for mc2 ops on A2 (#3015)

2025-10-13 16:13:17 +08:00

__init__.py

[SpecDecode] Add spec decode support (#500)

2025-04-17 20:16:32 +08:00