MidnightSun f4871c6ab9 [Kernel] add triton kernels for sampling (#4550) ...

### What this PR does / why we need it?
Replace pyorch implement of sampling with triton kernels

### Does this PR introduce _any_ user-facing change?
No


- vLLM version: v0.11.2

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Signed-off-by: Lord_of_Ironhill <suiweiyi@huawei.com>
Signed-off-by: whx-sjtu <2952154980@qq.com>
Co-authored-by: Lord_of_Ironhill <suiweiyi@huawei.com>
Co-authored-by: whx-sjtu <2952154980@qq.com>

2025-12-01 17:41:58 +08:00

..

logits_processor

[main] add pd transfer for ascend scheduler (#2753)

2025-09-10 08:46:39 +08:00

__init__.py

Spec decode support for V1 Engine (#874)

2025-05-23 14:25:46 +08:00

rejection_sampler.py

[Kernel] add triton kernels for sampling (#4550)

2025-12-01 17:41:58 +08:00

sampler.py

[refact] unified soc_version code (#4359)

2025-11-26 14:28:55 +08:00