0617d7d394
### What this PR does / why we need it?
1.Add the implementation of normal Aclnn operators: MoeCombineNormal,
MoeDispatchNormal, NotifyDispatch，and DispatchLayout.
- MoeCombineNormal: Implements the combine logic within MoE operations.
- MoeDispatchNormal: Implements the dispatch logic within MoE
operations.
- NotifyDispatch: Exchanges topk_idx information among different ranks
to calculate the device memory required for the dispatch stage.
- DispatchLayout: Used to calculate information related to the device
memory layout for the dispatch stage.
2.Provide PyTorch interfaces for normal operators—get_dispatch_layout,
dispatch_prefill, and combine_prefill—to be used for MoE communication
during the prefill stage in vLLM.
- get_dispatch_layout: Calculates information related to the device
memory layout for the dispatch operator, and is called before
dispatch_prefill.
- dispatch_prefill: Initiates the dispatch operation.
- combine_prefill: Initiates the combine operation.
### Does this PR introduce _any_ user-facing change?
No
### How was this patch tested?
The functionality has already been validated using the local Qwen model.
Test cases will be added after support for multi-NPU use cases in the CI
pipeline is finalized.
- vLLM version: v0.12.0
- vLLM main:
ad32e3e19c
Signed-off-by: shiro-zzzz <zhangdianhao@huawei.com>
68 lines
2.1 KiB
C++
68 lines
2.1 KiB
C++
#ifndef CAM_DATACOPY_GM2GM_H
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#define CAM_DATACOPY_GM2GM_H
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#include <type_traits>
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#include "comm_args.h"
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using namespace AscendC;
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using namespace Moe;
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template <typename T>
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FORCE_INLINE_AICORE void SetAtomicOpType(int op)
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{
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switch (op) {
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case ADD:
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AscendC::SetAtomicAdd<T>();
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break;
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case MUL:
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// Ignore setting the atomic register when performing mul
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break;
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case MAX:
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AscendC::SetAtomicMax<T>();
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break;
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case MIN:
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AscendC::SetAtomicMin<T>();
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break;
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default:
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AscendC::SetAtomicNone();
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}
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}
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template <typename T>
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FORCE_INLINE_AICORE void CpUB2GM(__gm__ T *gmAddr, __ubuf__ T *ubAddr, uint32_t size)
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{
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LocalTensor<uint8_t> ubTensor;
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GlobalTensor<uint8_t> gmTensor;
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DataCopyExtParams dataCopyParams(1, size, 0, 0, 0);
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ubTensor.address_.logicPos = static_cast<uint8_t>(TPosition::VECIN);
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ubTensor.address_.bufferAddr = reinterpret_cast<uint64_t>(ubAddr);
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gmTensor.SetGlobalBuffer(reinterpret_cast<__gm__ uint8_t *>(gmAddr));
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DataCopyPad(gmTensor, ubTensor, dataCopyParams);
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}
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template <typename T>
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FORCE_INLINE_AICORE void CpGM2UB(__ubuf__ T *ubAddr, __gm__ T *gmAddr, uint32_t size)
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{
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LocalTensor<uint8_t> ubTensor;
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GlobalTensor<uint8_t> gmTensor;
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DataCopyExtParams dataCopyParams(1, size, 0, 0, 0);
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ubTensor.address_.logicPos = static_cast<uint8_t>(TPosition::VECIN);
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ubTensor.address_.bufferAddr = reinterpret_cast<uint64_t>(ubAddr);
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gmTensor.SetGlobalBuffer(reinterpret_cast<__gm__ uint8_t *>(gmAddr));
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DataCopyPadExtParams<uint8_t> padParams;
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DataCopyPad(ubTensor, gmTensor, dataCopyParams, padParams);
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}
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template<typename T>
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FORCE_INLINE_AICORE void CopyUB2UB(__ubuf__ T *dst, __ubuf__ T *src, const uint32_t calCount)
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{
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LocalTensor<T> srcTensor;
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LocalTensor<T> dstTensor;
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TBuffAddr srcAddr, dstAddr;
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srcAddr.bufferAddr = reinterpret_cast<uint64_t>(src);
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dstAddr.bufferAddr = reinterpret_cast<uint64_t>(dst);
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srcTensor.SetAddr(srcAddr);
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dstTensor.SetAddr(dstAddr);
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DataCopy(dstTensor, srcTensor, calCount);
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}
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#endif // CAM_DATACOPY_GM2GM_H
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