2 Commits

Author	SHA1	Message	Date
jiangyunfan1	80b8df881f	[TEST] Add Qwen3-32b-w8a8 acc/perf A2/A3 test (#3541) ... ### What this PR does / why we need it? This PR Qwen3-32b-w8a8 acc/perf 8 cases on A2 and A3, we need test them daily. ### Does this PR introduce _any_ user-facing change? No ### How was this patch tested? by running the test - vLLM version: v0.11.0rc3 - vLLM main: https://github.com/vllm-project/vllm/commit/v0.11.0 --------- Signed-off-by: jiangyunfan1 <jiangyunfan1@h-partners.com> Signed-off-by: wangli <wangli858794774@gmail.com> Signed-off-by: Yikun Jiang <yikunkero@gmail.com> Signed-off-by: root <root@hostname-2pbfv.foreman.pxe> Co-authored-by: wangli <wangli858794774@gmail.com> Co-authored-by: Yikun Jiang <yikunkero@gmail.com>	2025-10-21 17:34:48 +08:00
jiangyunfan1	9e59fc1510	[TEST] Add initial aisbench support and Qwen3 32B acc/perf test (#3474) ... ### What this PR does / why we need it? This PR adds the first aisbench case for nightly test, it lays a foundation for following performance and accuracy tests in nightly test. ### Does this PR introduce _any_ user-facing change? No ### How was this patch tested? By running the test - vLLM version: v0.11.0rc3 - vLLM main: https://github.com/vllm-project/vllm/commit/v0.11.0 Signed-off-by: Yikun Jiang <yikunkero@gmail.com> Co-authored-by: jiangyunfan1 <jiangyunfan1@h-partners.com>	2025-10-20 09:33:17 +08:00