From c0e12143a3919ec2d980be9891344fa893442a13 Mon Sep 17 00:00:00 2001 From: wangxiyuan Date: Wed, 27 Aug 2025 11:24:35 +0800 Subject: [PATCH] [CI] Fix UT failure (#2563) UT is broken by vLLM commit https://github.com/vllm-project/vllm/pull/23664 This PR mock the related config to recover the CI - vLLM version: v0.10.1.1 - vLLM main: https://github.com/vllm-project/vllm/commit/6dab89b8ece7e022bd3df5774c9ddf309e2eb2d9 Signed-off-by: wangxiyuan --- tests/ut/core/test_scheduler.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/ut/core/test_scheduler.py b/tests/ut/core/test_scheduler.py index 635e08d..5c793d1 100644 --- a/tests/ut/core/test_scheduler.py +++ b/tests/ut/core/test_scheduler.py @@ -135,6 +135,8 @@ class TestAscendScheduler(TestBase): ) model_config.pooler_config = MagicMock() model_config.multimodal_config = MagicMock() + model_config.hf_config = MagicMock() + model_config.hf_config.is_encoder_decoder = False # Cache config, optionally force APC kwargs_cache: Dict[str, Any] = ({} if ENABLE_PREFIX_CACHING is None else {