[FOLLOWUP] Use base test to avoid patch everwhere (#1634)

### What this PR does / why we need it?
Use base test to avoid patch everwhere.

Followup here: https://github.com/vllm-project/vllm-ascend/pull/1566

### Does this PR introduce _any_ user-facing change?
No

### How was this patch tested?
ut ci passed

- vLLM version: v0.9.2
- vLLM main:
8d0a01a5f2

Signed-off-by: Yikun Jiang <yikunkero@gmail.com>
This commit is contained in:
Yikun Jiang
2025-07-22 09:03:40 +08:00
committed by GitHub
parent 33e1ea4d1a
commit 5f0b42e414
8 changed files with 18 additions and 24 deletions

View File

@@ -1,9 +1,9 @@
import unittest
import zlib
from unittest.mock import MagicMock
import torch
from tests.ut.base import TestBase
from vllm_ascend.distributed.kv_transfer.simple_buffer import (SimpleBuffer,
int32_hash)
@@ -17,7 +17,7 @@ class MockSimplePipe:
self.deallocate_buffer = MagicMock()
class TestSimpleBuffer(unittest.TestCase):
class TestSimpleBuffer(TestBase):
def setUp(self):
self.pipe = MockSimplePipe()