[Ops] Add layernorm for qwen3Next (#5765)
### What this PR does / why we need it?
Add layernormFn triton op for qwen3Next model for better performance.
<img width="248" height="526" alt="image"
src="https://github.com/user-attachments/assets/27b47157-5df5-4db1-aa88-1dae799b2bf6"
/>
### Does this PR introduce _any_ user-facing change?
No
### How was this patch tested?
- vLLM version: v0.13.0
- vLLM main:
2f4e6548ef
---------
Signed-off-by: SunnyLee219 <3294305115@qq.com>
This commit is contained in:
2
.github/workflows/nightly_test_a2.yaml
vendored
2
.github/workflows/nightly_test_a2.yaml
vendored
@@ -54,7 +54,7 @@ jobs:
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tests: tests/e2e/nightly/single_node/models/test_qwen3_8b.py
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tests: tests/e2e/nightly/single_node/models/test_qwen3_8b.py
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- name: qwen3next
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- name: qwen3next
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os: linux-aarch64-a2-4
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os: linux-aarch64-a2-4
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ests: tests/e2e/nightly/single_node/models/test_qwen3_next.py
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tests: tests/e2e/nightly/single_node/models/test_qwen3_next.py
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- name: qwen3-32b
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- name: qwen3-32b
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os: linux-aarch64-a2-4
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os: linux-aarch64-a2-4
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tests: tests/e2e/nightly/single_node/models/test_qwen3_32b.py
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tests: tests/e2e/nightly/single_node/models/test_qwen3_32b.py
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@@ -18,9 +18,10 @@
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from typing import Optional, Tuple, Union
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from typing import Optional, Tuple, Union
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import torch
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import torch
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from torch import nn
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from vllm.config import get_current_vllm_config
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from vllm.config import get_current_vllm_config
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from vllm.model_executor.layers.layernorm import GemmaRMSNorm, RMSNorm
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from vllm.model_executor.layers.layernorm import GemmaRMSNorm, RMSNorm, RMSNormGated
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from vllm_ascend.ops.triton.layernorm_gated import layer_norm_fwd_npu
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class AscendRMSNorm(RMSNorm):
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class AscendRMSNorm(RMSNorm):
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@@ -95,3 +96,80 @@ class AscendGemmaRMSNorm(GemmaRMSNorm):
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x, _ = torch_npu.npu_rms_norm(x, 1.0 + self.weight,
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x, _ = torch_npu.npu_rms_norm(x, 1.0 + self.weight,
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self.variance_epsilon)
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self.variance_epsilon)
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return x
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return x
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class LayerNormFn(torch.autograd.Function):
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@staticmethod
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def forward(ctx,
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x,
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weight,
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bias,
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z=None,
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eps=1e-6,
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group_size=None,
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norm_before_gate=True,
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is_rms_norm=False):
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"""If z is not None, we do norm(x) * silu(z) if norm_before_gate, else norm(x * silu(z))
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"""
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x_shape_og = x.shape
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# reshape input data into 2D tensor
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x = x.reshape(-1, x.shape[-1])
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if x.stride(-1) != 1:
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x = x.contiguous()
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if z is not None:
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assert z.shape == x_shape_og
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z = z.reshape(-1, z.shape[-1])
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if z.stride(-1) != 1:
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z = z.contiguous()
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weight = weight.contiguous()
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if bias is not None:
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bias = bias.contiguous()
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y, mean, rstd = layer_norm_fwd_npu(
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x,
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weight,
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bias,
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eps,
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z=z,
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group_size=group_size,
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norm_before_gate=norm_before_gate,
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is_rms_norm=is_rms_norm,
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)
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ctx.save_for_backward(x, weight, bias, mean, rstd, z)
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ctx.x_shape_og = x_shape_og
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ctx.eps = eps
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ctx.group_size = group_size
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ctx.norm_before_gate = norm_before_gate
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ctx.is_rms_norm = is_rms_norm
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return y.reshape(x_shape_og)
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class AscendRMSNormGated(RMSNormGated):
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def __init__(
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self,
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hidden_size,
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eps: float = 1e-5,
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group_size: Optional[int] = None,
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norm_before_gate: bool = False,
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device: Optional[torch.device] = None,
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dtype: Optional[torch.dtype] = None,
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):
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"""If group_size is not None, we do GroupNorm with each group having group_size elements.
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group_size=None is equivalent to group_size=hidden_size (i.e. there's only 1 group).
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"""
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factory_kwargs = {"device": device, "dtype": dtype}
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super().__init__(hidden_size, eps, group_size, norm_before_gate, device, dtype)
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self.eps = eps
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self.weight = nn.Parameter(torch.empty(hidden_size, **factory_kwargs))
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self.register_parameter("bias", None)
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self.group_size = group_size
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self.norm_before_gate = norm_before_gate
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self.reset_parameters()
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def reset_parameters(self):
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torch.nn.init.ones_(self.weight)
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def forward_oot(self, x, z=None):
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"""If z is not None, we do norm(x) * silu(z) if norm_before_gate, else norm(x * silu(z))
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"""
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return LayerNormFn.apply(x, self.weight, self.bias, z, self.eps, self.group_size,
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self.norm_before_gate, True)
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171
vllm_ascend/ops/triton/layernorm_gated.py
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171
vllm_ascend/ops/triton/layernorm_gated.py
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@@ -0,0 +1,171 @@
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# Adapt from https://github.com/fla-org/flash-linear-attention/blob/main/fla/modules/layernorm_gated.py
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# Copyright (c) 2024, Tri Dao.
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# Based on the Triton LayerNorm tutorial: https://triton-lang.org/main/getting-started/tutorials/05-layer-norm.html
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# For the backward pass, we keep weight_grad and bias_grad in registers and accumulate.
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# This backward pass is faster for dimensions up to 8k, but after that it's much slower due to register spilling.
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# The models we train have hidden dim up to 8k anyway (e.g. Llama 70B), so this is fine.
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# mypy: ignore-errors
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import torch
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from vllm.triton_utils import tl, triton
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@triton.heuristics({"HAS_BIAS": lambda args: args["B"] is not None})
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@triton.heuristics({"HAS_Z": lambda args: args["Z"] is not None})
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@triton.jit
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def _layer_norm_fwd_1pass_kernel_npu(
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X, # pointer to the input
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Y, # pointer to the output
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W, # pointer to the weights
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B, # pointer to the biases
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Z, # pointer to the other branch
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Mean, # pointer to the mean
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Rstd, # pointer to the 1/std
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stride_x_row, # how much to increase the pointer when moving by 1 row
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stride_y_row,
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stride_z_row,
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M, # number of rows in X
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N, # number of columns in X
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eps, # epsilon to avoid division by zero
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BLOCK_M: tl.constexpr,
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BLOCK_N: tl.constexpr,
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HAS_BIAS: tl.constexpr,
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HAS_Z: tl.constexpr,
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NORM_BEFORE_GATE: tl.constexpr,
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IS_RMS_NORM: tl.constexpr,
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):
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# Map the program id to the row of X and Y it should compute.
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pid_m = tl.program_id(0)
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group = tl.program_id(1)
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if not IS_RMS_NORM:
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Mean += group * M
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Rstd += group * M
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W += group * N
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if HAS_BIAS:
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B += group * N
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# Compute row indices for this program
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rows = pid_m * BLOCK_M + tl.arange(0, BLOCK_M)
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cols = tl.arange(0, BLOCK_N)
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# Mask for valid rows and cols
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row_mask = rows < M
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col_mask = cols < N
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# Load weight once (broadcasted over rows)
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w = tl.load(W + cols, mask=col_mask).to(tl.float32)
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if HAS_BIAS:
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b = tl.load(B + cols, mask=col_mask).to(tl.float32)
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# Load X: shape [BLOCK_M, BLOCK_N]
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x_ptrs = X + rows[:, None] * stride_x_row + cols[None, :] + group * N
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x = tl.load(x_ptrs, mask=row_mask[:, None] & col_mask[None, :]).to(tl.float32)
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# Load Z if needed
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if HAS_Z:
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z_ptrs = Z + rows[:, None] * stride_z_row + cols[None, :] + group * N
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z = tl.load(z_ptrs, mask=row_mask[:, None] & col_mask[None, :]).to(tl.float32)
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if not NORM_BEFORE_GATE:
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x *= z * tl.sigmoid(z)
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# Compute statistics per row
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if not IS_RMS_NORM:
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mean = tl.sum(x, axis=1) / N # [BLOCK_M]
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xbar = tl.where(col_mask[None, :], x - mean[:, None], 0.0)
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var = tl.sum(xbar * xbar, axis=1) / N
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tl.store(Mean + rows, mean, mask=row_mask)
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else:
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xbar = tl.where(col_mask[None, :], x, 0.0)
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var = tl.sum(xbar * xbar, axis=1) / N
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rstd = 1.0 / tl.sqrt(var + eps) # [BLOCK_M]
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tl.store(Rstd + rows, rstd, mask=row_mask)
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# Normalize
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if not IS_RMS_NORM:
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x_hat = (x - mean[:, None]) * rstd[:, None]
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else:
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x_hat = x * rstd[:, None]
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y = x_hat * w[None, :]
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if HAS_BIAS:
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y += b[None, :]
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# Post-gate
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if HAS_Z and NORM_BEFORE_GATE:
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y *= z * tl.sigmoid(z)
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# Store output
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y_ptrs = Y + rows[:, None] * stride_y_row + cols[None, :] + group * N
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tl.store(y_ptrs, y, mask=row_mask[:, None] & col_mask[None, :])
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def layer_norm_fwd_npu(
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x,
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weight,
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bias,
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eps,
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z=None,
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out=None,
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group_size=None,
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norm_before_gate=True,
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is_rms_norm=False,
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):
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M, N = x.shape
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if group_size is None:
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group_size = N
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assert N % group_size == 0
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ngroups = N // group_size
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assert x.stride(-1) == 1
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if z is not None:
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assert z.stride(-1) == 1
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assert z.shape == (M, N)
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assert weight.shape == (N,)
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assert weight.stride(-1) == 1
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if bias is not None:
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assert bias.stride(-1) == 1
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assert bias.shape == (N,)
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# allocate output
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if out is not None:
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assert out.shape == x.shape
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else:
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out = torch.empty_like(x)
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assert out.stride(-1) == 1
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mean = (
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torch.empty((ngroups * M,), dtype=torch.float32, device=x.device)
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if not is_rms_norm
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else None
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)
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rstd = torch.empty((ngroups * M,), dtype=torch.float32, device=x.device)
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MAX_FUSED_SIZE = 65536 // x.element_size()
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BLOCK_N = min(MAX_FUSED_SIZE, triton.next_power_of_2(group_size))
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if group_size > BLOCK_N:
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raise RuntimeError("Feature dim too large.")
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# Choose BLOCK_M: e.g., 16, 32, 64 — depends on NPU vector core capacity
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BLOCK_M = 64 # Tune this based on your NPU's register/shared memory
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# Now grid is (num blocks over M, num groups)
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grid = (triton.cdiv(M, BLOCK_M), ngroups)
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_layer_norm_fwd_1pass_kernel_npu[grid](
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x,
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out,
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weight,
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bias,
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z,
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mean,
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rstd,
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x.stride(0),
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out.stride(0),
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z.stride(0) if z is not None else 0,
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M,
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group_size,
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eps,
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BLOCK_M=BLOCK_M,
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BLOCK_N=BLOCK_N,
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NORM_BEFORE_GATE=norm_before_gate,
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IS_RMS_NORM=is_rms_norm,
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# Remove multibuffer if not needed
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)
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return out, mean, rstd
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@@ -669,7 +669,7 @@ def register_ascend_customop(vllm_config: VllmConfig | None = None):
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from vllm_ascend.ops.activation import AscendQuickGELU, AscendSiluAndMul
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from vllm_ascend.ops.activation import AscendQuickGELU, AscendSiluAndMul
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from vllm_ascend.ops.fused_moe.fused_moe import AscendFusedMoE, AscendSharedFusedMoE
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from vllm_ascend.ops.fused_moe.fused_moe import AscendFusedMoE, AscendSharedFusedMoE
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from vllm_ascend.ops.layernorm import AscendGemmaRMSNorm, AscendRMSNorm
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from vllm_ascend.ops.layernorm import AscendGemmaRMSNorm, AscendRMSNorm, AscendRMSNormGated
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from vllm_ascend.ops.linear import (
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from vllm_ascend.ops.linear import (
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AscendColumnParallelLinear,
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AscendColumnParallelLinear,
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AscendMergedColumnParallelLinear,
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AscendMergedColumnParallelLinear,
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@@ -715,6 +715,7 @@ def register_ascend_customop(vllm_config: VllmConfig | None = None):
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"MultiHeadLatentAttentionWrapper": AscendMultiHeadLatentAttention,
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"MultiHeadLatentAttentionWrapper": AscendMultiHeadLatentAttention,
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"MMEncoderAttention": AscendMMEncoderAttention,
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"MMEncoderAttention": AscendMMEncoderAttention,
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"ApplyRotaryEmb": AscendApplyRotaryEmb,
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"ApplyRotaryEmb": AscendApplyRotaryEmb,
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"RMSNormGated": AscendRMSNormGated,
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}
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}
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# 310P: override selected ops with 310P implementations (keep minimal changes outside _310p)
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# 310P: override selected ops with 310P implementations (keep minimal changes outside _310p)
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