li haoyang
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28d4d47280
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[Feature] Integrate quick allreduce and select the best allreduce implementation (#6619)
Signed-off-by: Haoyang Li <Haoyang.Li@amd.com>
Co-authored-by: ilmarkov <imarkov@redhat.com>
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2025-07-24 20:48:42 -07:00 |
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Yijie Zhu
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a39d928782
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support qwen2 running on ascend npu device (#7022)
Co-authored-by: 刁莹煜 <diaoyingyu1@hisilicon.com>
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2025-06-17 11:24:10 -07:00 |
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zyksir
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8e3797be1c
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support 1 shot allreduce in 1-node and 2-node using mscclpp (#6277)
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2025-06-04 22:11:24 -07:00 |
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Lianmin Zheng
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e8e18dcdcc
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Revert "fix some typos" (#6244)
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2025-05-12 12:53:26 -07:00 |
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applesaucethebun
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d738ab52f8
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fix some typos (#6209)
Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca>
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2025-05-13 01:42:38 +08:00 |
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Lianmin Zheng
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177320a582
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Clean up imports (#5467)
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2025-04-16 15:26:49 -07:00 |
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Yi Zhang
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aba5ca154d
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python transfer custom allreduce from trt kernel to vllm kernel (#5080)
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2025-04-05 15:35:55 -07:00 |
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Yineng Zhang
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c787298547
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use sgl custom all reduce (#4441)
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2025-03-18 00:46:41 -07:00 |
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Lianmin Zheng
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aa957102a9
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Simplify tests & Fix trtllm custom allreduce registration (#4252)
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2025-03-10 01:24:22 -07:00 |
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Lianmin Zheng
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8abf74e3c9
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Rename files in sgl kernel to avoid nested folder structure (#4213)
Co-authored-by: zhyncs <me@zhyncs.com>
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2025-03-08 22:54:51 -08:00 |
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kk
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e0a2c96308
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Fix breakage problem when using custom_ar (#4052)
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2025-03-04 02:59:03 -08:00 |
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Lianmin Zheng
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a3ab768a2b
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Clean up custom allreduce (#4029)
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2025-03-03 04:59:53 -08:00 |
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Hubert Lu
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9cf4077294
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Enable custom AR for AMD GPUs and maintain it in sgl-kernel (#3406)
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2025-03-02 15:19:06 -08:00 |
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Lianmin Zheng
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89cd923581
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Roll back to use vllm custom allreduce (#3006)
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2025-01-20 04:03:15 -08:00 |
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yizhang2077
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24cafe3177
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add config to swtich from vllm custom allreduce to sgl_kernel custom allreduce (#2981)
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2025-01-19 22:30:38 +08:00 |
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yizhang2077
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767c9dec03
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adapt custom allreduce for tensorrt llm (#2511)
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2025-01-16 04:57:35 +08:00 |
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yizhang2077
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d5b95cbb53
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adapt vllm distributed module to sglang (#2244)
Co-authored-by: Yineng Zhang <me@zhyncs.com>
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2024-12-01 15:54:52 +08:00 |
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