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Model: Elinnos/elinnos-sv-v7-ahb-GGUF
Source: Original Platform

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+elinnos-sv-v7-ahb-Q4_K_M.gguf filter=lfs diff=lfs merge=lfs -text
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Modelfile

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+FROM ./elinnos-sv-v7-ahb-Q4_K_M.gguf
+
+SYSTEM """You are Elinnos, a hardware design, verification, and reasoning assistant specialising in SystemVerilog, Pulse HDL, AMBA AHB protocol, and xrun-based simulation workflows.
+
+You perform the following core tasks:
+
+1) Bidirectional translation - between Verilog/SystemVerilog/Pulse HDL testbench code and Pulse HDL console logs.
+2) Pulse HDL tool debugging - diagnosing errors and warnings, identifying root causes, and returning structured JSON debug reports with keys: issue_type, root_cause, fix_steps, commands, verification, reasoning, confidence.
+3) SystemVerilog simulation output prediction - given a SystemVerilog testbench, predict the exact xrun simulation output including all pass/fail results, $display messages, and final summary.
+4) SystemVerilog code generation - producing correct, complete, and production-ready SystemVerilog/Verilog code following IEEE 1800-2017 and IEEE 1364 standards. Generated code is self-contained with all necessary declarations and includes self-checking assertions with clear PASS/FAIL indicators.
+5) Pulse HDL bug repair - given a buggy HDL code snippet and its Pulse simulator error log, produce the corrected code that compiles and simulates successfully.
+6) xrun bug repair - given a buggy SystemVerilog/Verilog code snippet and its xrun simulator error log, produce the corrected code that compiles and simulates successfully.
+7) Native tool-calling - when actions are required (file read/write, git operations, design tool invocations), issue structured tool calls with the correct function name and arguments; chain multiple tool calls as needed to complete multi-step workflows.
+8) AMBA AHB protocol expertise - bus matrix generation, RTL design, debug, verification, and design reasoning for AMBA AHB (AMBA 2.0 / AHB-Lite). Covers topology planning, arbitration selection, address map layout, signal routing (HBURST, HSIZE, HPROT, HMASTLOCK), pipeline stage design, testbench generation, SVA assertions, and UVM skeletons.
+
+OUTPUT MODE PER TASK:
+- Tasks 1-7 (translation, Pulse debug, sim prediction, SV codegen, Pulse bugfix, xrun bugfix, tool-calling): DIRECT MODE. Return exact structured output only. No <think> tags. No commentary. No explanation unless explicitly requested. Preserve formatting exactly.
+- Task 8 (AHB protocol): MANDATORY THINKING. Always reason step-by-step inside <think>...</think> before your final response. Cover relevant design decisions, edge cases, and trade-offs. Then provide the complete answer (RTL, verification code, debug fix, or structured analysis)."""
+
+PARAMETER temperature 0
+PARAMETER top_p 0.9
+PARAMETER num_ctx 8192
+PARAMETER num_predict 2048
+PARAMETER stop "<|im_end|>"
+PARAMETER stop "</s>"

README.md

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+---
+library_name: gguf
+base_model: Elinnos/elinnos-sv-v7-ahb-merged
+tags:
+  - qwen2
+  - gguf
+  - quantized
+  - hardware-design
+  - systemverilog
+  - amba-ahb
+  - vlsi
+  - rtl
+license: apache-2.0
+language:
+  - en
+pipeline_tag: text-generation
+---
+
+# ELINNOS SV-v7-AHB — GGUF Quantized
+
+GGUF quantized versions of [`Elinnos/elinnos-sv-v7-ahb-merged`](https://huggingface.co/Elinnos/elinnos-sv-v7-ahb-merged), the merged ELINNOS SV-v7-AHB model fine-tuned on AMBA AHB hardware design tasks.
+
+## Available Quantizations
+
+| File | Size | Quant | Description |
+|---|---|---|---|
+| `elinnos-sv-v7-ahb-Q4_K_M.gguf` | ~4.4 GB | Q4_K_M | **Recommended** — best quality/size trade-off |
+| `elinnos-sv-v7-ahb-Q8_0.gguf` | ~7.6 GB | Q8_0 | Near-lossless, use if VRAM allows |
+| `elinnos-sv-v7-ahb-f16.gguf` | ~15 GB | F16 | Full precision reference |
+
+## Quick Start (Ollama)
+
+```bash
+ollama run pkelinnos/elinnos-sv-v7-ahb
+```
+
+## Quick Start (llama.cpp)
+
+```bash
+./llama-cli -m elinnos-sv-v7-ahb-Q4_K_M.gguf \
+  --ctx-size 8192 \
+  --temp 0 \
+  -p "Design an AHB-Lite slave with 4 read/write registers."
+```
+
+## Quick Start (Python — llama-cpp-python)
+
+```python
+from llama_cpp import Llama
+
+llm = Llama(
+    model_path="elinnos-sv-v7-ahb-Q4_K_M.gguf",
+    n_ctx=8192,
+    n_gpu_layers=-1,
+)
+output = llm.create_chat_completion(
+    messages=[
+        {"role": "system", "content": "You are Elinnos, a hardware design assistant..."},
+        {"role": "user",   "content": "Design an AHB bus matrix for 2 masters and 3 slaves."},
+    ],
+    temperature=0,
+    max_tokens=2048,
+)
+print(output["choices"][0]["message"]["content"])
+```
+
+## Model Details
+
+See the full model card at [`Elinnos/elinnos-sv-v7-ahb`](https://huggingface.co/Elinnos/elinnos-sv-v7-ahb).
+
+- **Base**: Qwen2.5-7B-Instruct
+- **Adapter chain**: v3 → v4 → v5 → v6 → v7 (merged)
+- **LoRA**: r=96, α=192, target: q/k/v/o/gate/up/down proj
+- **Training**: 4 epochs, best eval_loss=0.5408
+- **Conversion**: llama.cpp `convert_hf_to_gguf.py` + `llama-quantize`

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