---
license: apache-2.0
license_link: https://huggingface.co/AS-SiliconMind/SiliconMind-V1-Qwen3-4B-T-2507-76k/blob/main/LICENSE
language:
- en
base_model:
- Qwen/Qwen3-4B-Thinking-2507
pipeline_tag: text-generation
tags:
- verilog
- reasoning
- multi-agent
---

<p align="center">
  <img alt="SiliconMind Logo" src="https://raw.githubusercontent.com/AS-SiliconMind/SiliconMind-V1/refs/heads/gh-pages/images/logo.webp"/>
</p>

# SiliconMind-V1-Qwen3-4B-T-2507-76k: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation

## Model Overview
**SiliconMind-V1** is a family of open-source Large Language Models (LLMs) specialized for Verilog code generation, testing, and debugging. Unlike previous approaches that rely heavily on commercial models or external EDA tools, SiliconMind-V1 is locally fine-tuned to iteratively **generate**, **test**, and **debug** RTL designs through test-time scaling.

The **SiliconMind-V1** models are enabled by a unified multi-agent framework for reasoning-oriented training data generation with integrated testbench-driven verification to achieve state-of-the-art functional correctness on major benchmarks.

**This release** — `SiliconMind-V1-Qwen3-4B-T-2507-76k` — is fine-tuned from `Qwen3-4B-Thinking-2507` on an expanded **76k**-sample training mix (vs. the 36k mix used for the original [`SiliconMind-V1-Qwen3-4B-T-2507`](https://huggingface.co/AS-SiliconMind/SiliconMind-V1-Qwen3-4B-T-2507) release). Benchmark numbers for this variant will be added once evaluation completes.

**Key Features:**
* **Reasoning-Oriented:** Trained to "think" before coding, producing reasoning traces that guide functional correctness.
* **Self-Testing & Debugging:** Capable of generating its own test report to fix bugs without tool-calling.
* **Tool-Free Verification:** Reduces reliance on expensive, proprietary EDA software during the generation loop.
* **Multi-Strategy Inference:** Supports Regular, Deep Thinking, and Agentic inference modes for scalable performance.

## Model Variants
We provide SiliconMind-V1 variants fine-tuned from the following base models:

| Model Name | Base Model | Size |
|:---|:---|:---|
| [SiliconMind-V1-Qwen2.5-C-7B-I](https://huggingface.co/AS-SiliconMind/SiliconMind-V1-Qwen2.5-C-7B-I) | Qwen2.5-Coder-7B-Instruct | 7B |
| [SiliconMind-V1-Qwen3-4B-T-2507](https://huggingface.co/AS-SiliconMind/SiliconMind-V1-Qwen3-4B-T-2507) | Qwen3-4B-Thinking-2507 | 4B |
| [**SiliconMind-V1-Qwen3-4B-T-2507-76k**](https://huggingface.co/AS-SiliconMind/SiliconMind-V1-Qwen3-4B-T-2507-76k) *(this model — 76k training mix)* | Qwen3-4B-Thinking-2507 | 4B |
| [SiliconMind-V1-Qwen3-8B](https://huggingface.co/AS-SiliconMind/SiliconMind-V1-Qwen3-8B) | Qwen3-8B | 8B |
| [SiliconMind-V1-Olmo-3-7B-Think](https://huggingface.co/AS-SiliconMind/SiliconMind-V1-Olmo-3-7B-Think) | Olmo-3-7B-Think | 7B |

### Model Sources

- **Project Page:** https://AS-SiliconMind.github.io/SiliconMind-V1
- **Repositories:**
    - Inference Engine: https://github.com/AS-SiliconMind/SiliconMind-V1
- **Paper:** arxiv

## Usage & Inference Strategies

SiliconMind-V1 is designed to work with three distinct inference strategies, allowing users to trade off between latency/cost and accuracy. Please refer to our [inference engine](https://github.com/AS-SiliconMind/SiliconMind-V1) for more details on how to get started with **SiliconMind-V1**.

### 1. Regular Strategy
The model acts as a standard code generator but is prompted to produce a reasoning trace before the final code.
* **Best for:** Quick prototyping and simple modules.

### 2. Deep Thinking Strategy
Explicit instructions are given to the model to solve the problem by:
1.  Drafting an initial solution.
2.  Mentally "testing" it against scenarios.
3.  Self-debugging within the reasoning trace.
* **Best for:** Complex logic where single-pass generation often fails.

### 3. Agentic Strategy (Recommended for SOTA Results)
A multi-turn workflow where the model plays different "Agent" roles sequentially:
1.  **Solution Agent:** Generates initial code + reasoning.
2.  **Test Agent:** Generates a test report for the code.
3.  **Debug Agent:** Reviews the test report and fixes errors.
* **Performance:** Achieves the highest pass rates (Pass@1) by allowing iterative refinement (up to 3 interactions recommended).

## Training
This variant was trained on an expanded Multi-Faceted Dataset constructed via a custom two-phase pipeline:

* **Code Generation Phase:** A multi-agent system (Revision, Solution, Testbench, Verification Agents) synthesized **76k** functionally verified (problem, reasoning, code, testbench) tuples from public sources.

* **Self-Correction Phase:** The model was stress-tested against these problems. Hard samples (where the model failed) were augmented with "Test" and "Debug" curriculum, teaching the model how to write test reports and fix its own errors.

## Evaluation
Benchmark results for this 76k variant on RTLLM-v2, VerilogEval-v2, VerilogEval-v2-NTU, and CVDP-cid02&03 are pending and will be added to this card once evaluation completes. For the original 36k variant's numbers, see the [`SiliconMind-V1-Qwen3-4B-T-2507`](https://huggingface.co/AS-SiliconMind/SiliconMind-V1-Qwen3-4B-T-2507) model card.

## License
**SiliconMind-V1** is licensed under [Apache 2.0](https://huggingface.co/AS-SiliconMind/SiliconMind-V1-Qwen3-4B-T-2507-76k/blob/main/LICENSE).
<br>
The base model's license: [Qwen3-4B-Thinking-2507](https://huggingface.co/Qwen/Qwen3-4B-Thinking-2507/blob/main/LICENSE).

## Acknowledgements
We acknowledge the financial support from Academia Sinica's SiliconMind Project (AS-IAIA-114-M11). We also thank the National Center for High-Performance Computing (NCHC) for providing computational and storage resources, and Taipei-1 for providing H100 computing resources. In addition, we acknowledge financial support from the National Science and Technology Council.

## Citation

**BibTeX:**
```
@misc{Chen2026SiliconMindV1,
  title  = {{SiliconMind-V1}: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation},
  author = {Mu-Chi Chen and Yu-Hung Kao and Po-Hsuan Huang and Shao-Chun Ho 
            and Hsiang-Yu Tsou and I-Ting Wu and En-Ming Huang 
            and Yu-Kai Hung and Wei-Po Hsin and Cheng Liang 
            and Chia-Heng Tu and Shih-Hao Hung and H.T. Kung},
  year   = {2026},
  url    = {https://AS-SiliconMind.github.io/SiliconMind-V1}
}
```
